Wafer Debonding
8-Inch Wafer-Level Silicon Removal
Controlled 8-inch wafer-level debonding enables intact large-area transfer with yield above 95%, establishing a production foundation for subsequent compound-semiconductor and silicon-IC bonding.
Process is infrastructure. Hanhua places heterogeneous 3D integration at the core, supported by full-stack GaN epitaxy, to provide a new integrated manufacturing foundation for the post-Moore era.
Full Stack 3DIC
Wafer-level hybrid bonding closes the final gap in mixed-signal integration. Select a process stage to explore the path from wafer to volume production.
Wafer Debonding
Controlled 8-inch wafer-level debonding enables intact large-area transfer with yield above 95%, establishing a production foundation for subsequent compound-semiconductor and silicon-IC bonding.
3D Bonding
Room-temperature hybrid bonding delivers alignment precision below 500 nm, TSV compatibility and support for compound semiconductors, MEMS, lithium niobate and other materials.
Open PDK
Open DRC/LVS rule files, layout templates and simulation models, together with the world's first 8-inch CMOS-compatible Micro-LED PDK, lower the barrier to heterogeneous-integration design and verification.
One-stop Foundry
A unified flow from incoming epitaxy through silicon removal, bonding, packaging and testing supports prototypes, pilot runs and volume production.
Full Stack GaN
Defining the performance ceiling and providing a high-quality material foundation for 3D integration.
High-quality epitaxial materials form a solid foundation for heterogeneous integration.
Validate next-generation chips with Hanhua, from PDKs and process modules to one-stop foundry services.