Heterogeneous 3D Integration · Full Stack
Wafer-level hybrid bonding closes the final gap in mixed-signal integration and defines a new semiconductor paradigm for the post-Moore era.
- Non-destructive Silicon Removal
Controlled 8-inch wafer-level debonding and intact large-area transfer with process yield above 95%. - 3D Stacking
Room-temperature hybrid bonding with alignment precision below 200 nm, TSV compatibility and support for compound semiconductors, MEMS, lithium niobate and other heterogeneous materials. - Open PDK
Provides DRC/LVS design rules, layout templates and simulation models aligned with CMOS design flows. - One-stop Foundry
Epitaxial growth → front-end processing → hybrid bonding → non-destructive silicon removal → device testing, from prototypes and pilot runs to volume manufacturing, serving more than 90% of domestic design houses.
Full-stack heterogeneous 3D integration supports compound semiconductors, MEMS, lithium niobate and other materials, helping heterogeneous solutions reach volume production faster.
